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| Semiconductor January 1999 CT T ODU MEN E PR PLACE -7747 T 2 OLE RE 0-44 OBS ENDED 1-80 .com 110kHz, Operational MM ications arris l ECO h NO R ntral App entapp@ Transconductance Amplifier Array Ce :c Call or email CA3060 Features * Low Power Consumption as Low as 100mW Per Amplifier Description The CA3060 monolithic integrated circuit consists of an array of three independent Operational Transconductance Amplifiers (see Note). This type of amplifier has the generic characteristics of an operational voltage amplifier with the exception that the forward gain characteristic is best described by transconductance rather than voltage gain (open-loop voltage gain is the product of the transconductance and the load resistance, gMRL). When operated into a suitable load resistor and with provisions for feedback, these amplifiers are well suited for a wide variety of operational-amplifier and related applications. In addition, the extremely high output impedance makes these types particularly well suited for service in active filters. The three amplifiers in the CA3060 are identical push-pull Class A types which can be independently biased to achieve a wide range of characteristics for specific application. The electrical characteristics of each amplifier are a function of the amplifier bias current (IABC). This feature offers the system designer maximum flexibility with regard to output current capability, power consumption, slew rate, input resistance, input bias current, and input offset current. The linear variation of the parameters with respect to bias and the ability to maintain a constant DC level between input and output of each amplifier also makes the CA3060 suitable for a variety of nonlinear applications such as mixers, multipliers, and modulators. In addition, the CA3060 incorporates a unique Zener diode regulator system that permits current regulation below supply voltages normally associated with such systems. NOTE: Generic applications of the OTA are described in AN-6668. For improved input operating ranges, refer to CA3080 and CA3280 data sheets (File Nos. 475 and 1174) and application notes AN6668 and AN6818. [ /Title (CA30 60) /Subject (110k Hz, Operational Transc onductance Amplifier Array) /Autho r () /Keywords (Harris Semiconductor, triple, transco nductance amplifier, low power op amp, * Independent Biasing for Each Amplifier * High Forward Transconductance * Programmable Range of Input Characteristics * Low Input Bias and Input Offset Current * High Input and Output Impedance * No Effect on Device Under Output Short-Circuit Conditions * Zener Diode Bias Regulator Applications * For Low Power Conventional Operational Amplifier Applications * Active Filters * Comparators * Gyrators * Mixers * Modulators * Multiplexers * Multipliers * Strobing and Gating Functions * Sample and Hold Functions Pinout CA3060 (PDIP) TOP VIEW 1 2 3 4 5 6 7 8 + 16 OUTPUT NO. 1 15 BIAS NO. 1 14 NON-INV. INPUT NO. 1 13 INV. INPUT NO. 1 12 INV. INPUT NO. 2 + 11 NON-INV. INPUT NO. 2 10 BIAS NO. 2 9 OUTPUT NO. 2 AMP 2 + Part Number Information PART NUMBER CA3060E TEMP. RANGE (oC) -40 to 85 PACKAGE 16 Ld PDIP PKG. NO. E16.3 REGULATOR OUT REGULATOR IN V+ INV. INPUT NO. 3 NON-INV. INPUT NO. 3 BIAS NO. 3 OUTPUT NO. 3 V- BIAS REG. AMP 1 AMP 3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1999 File Number 537.4 3-1 CA3060 Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) . . . . . . . 36V (18V) Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VDifferential Input Voltage (Each Amplifier) . . . . . . . . . . . . . . . . . . 5V Input Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Amplifier Bias Current (Each Amplifier) . . . . . . . . . . . . . . . . . . . 2mA Bias Regulator Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA Output Short Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Thermal Information Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VSUPPLY = 15V AMPLIFIER BIAS CURRENT IABC = 1A IABC = 10A MAX MIN TYP 1 30 300 26 MAX MIN 150 IABC = 100A TYP 1 250 2500 240 MAX 5 1000 5000 UNITS mV nA nA A PARAMETER Input Offset Voltage (See Figure 1) Input Offset Current (See Figure 2) Input Bias Current (See Figures 3, 4) Peak Output Current (See Figures 5, 6) Peak Output Voltage (See Figure 7) Positive Negative Amplifier Supply Current (Each Amplifier) (See Figures 8, 9) Power Consumption (Each Amplifier) Input Offset Voltage Sensitivity (Note 3) Positive Negative Amplifier Bias Voltage (Note 4, See Figure 10) SYMBOL VIO IIO IIB IOM MIN - TYP 1 3 33 2.3 VOM+ VOMIA - 13.6 14.7 8.5 - - 13.6 14.7 85 - 12 12 - 13.6 14.7 850 1200 V V A P - 0.26 - - 2.6 - - 26 36 mW VIO/V+ VIO/VVABC - 1.5 20 0.54 - - 2 20 0.60 - - 2 30 0.66 150 150 - V/V V/V V DYNAMIC CHARACTERISTICS At 1kHz, Unless Otherwise Specified Forward Transconductance (Large Signal) (See Figures 11, 12) Common Mode Rejection Ratio Common Mode Input Voltage Range Slew Rate (Test Circuit) (See Figure 17) Open Loop (g21) Bandwidth (See Figure 13) g21 1.55 18 30 102 mS CMRR VICR SR BWOL +12 to -12 - 110 +13 to -14 0.1 20 - +12 to -12 - 110 +13 to -14 1 45 - 70 +12 to -12 - 90 +13 to -14 8 110 - dB V V/s kHz 3-2 CA3060 Electrical Specifications TA = 25oC, VSUPPLY = 15V (Continued) AMPLIFIER BIAS CURRENT IABC = 1A PARAMETER Input Impedance Components Resistance (See Figure 14) Capacitance at 1MHz Output Impedance Components Resistance (See Figure 15) Capacitance at 1MHz SYMBOL RI CI RO CO VZ ZZ MIN TYP 1600 2.7 200 4.5 MAX MIN IABC = 10A TYP 170 2.7 20 4.5 MAX MIN 10 IABC = 100A TYP 20 2.7 2 4.5 MAX UNITS k pF M pF ZENER BIAS REGULATOR CHARACTERISTICS I2 = 0.1mA Voltage (See Figure 16) Impedance NOTES: 3. Conditions for Input Offset Voltage Sensitivity: a. Bias current derived from the regulator with an appropriate resistor connected from Terminal 1 to the bias terminal on the amplifier under test V+ is reduced to +13V for V+ sensitivity and V- is reduced to -13V for V- sensitivity. b. V+ Sensitivity in VO ffset - VO ffset for +13V and -15V Supplies V V = ----------------------------------------------------------------------------------------------------------------------------- , 1V VO ffset - VO ffset for -13V and +15V Supplies V V = ----------------------------------------------------------------------------------------------------------------------------- . 1V Temperature Coefficient = 3mV/oC 6.2 6.7 200 7.9 300 V V- Sensitivity in 4. Temperature Coefficient; -2.2mV/oC (at VABC = 0.54, IABC = 1A); -2.1mV/oC (at VABC = 0.060V, IABC = 10A); -1.9mV/oC (at VABC = 0.66V, IABC = 100A) Schematic Diagram BIAS REGULATOR AND ONE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ZENER BIAS REGULATOR D4 2 Q10 1 D5 INVERTING INPUT (NOTE 5) NON-INVERTING INPUT (NOTE 6) AMPLIFIER BIAS INPUT (NOTE 7) Q4 Q6 D2 Q5 Q7 3 V+ + IABC Q1 Q2 Q8 Q3 D1 D3 OUTPUT (NOTE 8) 8 V- NOTES: 5. Inverting Input of Amplifiers 1, 2 and 3 is on Terminals 13, 12 and 4, respectively. 6. Non-inverting Input of Amplifiers 1, 2 and 3 is Terminals 14, 11 and 5, respectively. 7. Amplifier Bias Current of Amplifiers 1, 2 and 3 is on Terminals 15, 10 and 6, respectively. 8. Output of Amplifiers 1, 2 and 3 is on Terminals 16, 9 and 7, respectively. 3-3 CA3060 Typical Performance Curves 2.0 SUPPLY VOLTAGE: VS = 6 VS = 15 1.5 125oC 1.0 25oC -55oC 0.5 1000 MAXIMUM INPUT OFFSET CURRENT (nA) INPUT OFFSET VOLTAGE (mV) 100 TYPICAL 10 TA = 25oC SUPPLY VOLTAGE: VS = 6 VS = 15 0.0 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) 1 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) FIGURE 1. INPUT OFFSET VOLTAGE vs AMPLIFIER BIAS CURRENT 10 MAXIMUM INPUT BIAS CURRENT (A) FIGURE 2. INPUT OFFSET CURRENT vs AMPLIFIER BIAS CURRENT 10 SUPPLY VOLTAGE: VS = 6 VS = 15 IABC = 100A TYPICAL 1 INPUT BIAS CURRENT (A) 1.0 IABC = 10A 0.1 0.1 TA = 25oC SUPPLY VOLTAGE: VS = 6 VS = 15 IABC = 1A 0.01 -75 0.01 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 3. INPUT BIAS CURRENT vs AMPLIFIER BIAS CURRENT FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 1000 TYPICAL PEAK OUTPUT CURRENT (A) PEAK OUTPUT CURRENT (A) 1000 IABC = 100A IABC = 30A 100 IABC = 10A MINIMUM 100 IABC = 3A 10 IABC = 1A SUPPLY VOLTAGE: VS = 6 VS = 15 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) 10 TA = 25oC SUPPLY VOLTAGE: VS = 6 VS = 15 1 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) 1 -75 FIGURE 5. PEAK OUTPUT CURRENT vs AMPLIFIER BIAS CURRENT FIGURE 6. PEAK OUTPUT CURRENT vs TEMPERATURE 3-4 CA3060 Typical Performance Curves 14 13 12 PEAK OUTPUT VOLTAGE (V) 6 5 4 3 -3 -4 -5 -6 -12 -13 -14 -15 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) VOM- (MIN) 15V SUPPLY VOM- (TYP) 15V SUPPLY VOM- (TYP) 6V SUPPLY VOM+ (MIN) 6V SUPPLY VOM- (MIN) 6V SUPPLY VOM+ (TYP) 6V SUPPLY VOM+ (MIN) 15V SUPPLY AMPLIFIER SUPPLY CURRENT (A) VOM+ (TYP) 15V SUPPLY (Continued) 10,000 TA = 25oC SUPPLY VOLTAGE: VS = 6 VS = 15 1000 MAXIMUM TYPICAL 100 10 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) FIGURE 7. PEAK OUTPUT VOLTAGE vs AMPLIFIER BIAS CURRENT FIGURE 8. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER) vs AMPLIFIER BIAS CURRENT 800 1000 AMPLIFIER SUPPLY CURRENT (A) IABC = 100A AMPLIFIER BIAS VOLTAGE (mV) SUPPLY VOLTAGE: VVS = 6 VS = 15 750 IABC = 30A 100 IABC = 10A 700 650 IABC = 3A 10 IABC = 1A SUPPLY VOLTAGE: V+ = 6V, V- = -6V V+ = 15V, V- = -15V 1 -75 -50 -25 0 25 50 75 100 125 600 550 500 1 10 100 1000 TEMPERATURE (oC) AMPLIFIER BIAS CURRENT (A) FIGURE 9. AMPLIFIER SUPPLY CURRENT (EACH AMPLIFIER) vs TEMPERATURE FIGURE 10. AMPLIFIER BIAS VOLTAGE vs AMPLIFIER BIAS CURRENT 1000 FORWARD TRANSCONDUCTANCE (mS) 100 TYPICAL FORWARD TRANSCONDUCTANCE (S) TA = 25oC, f = 1kHz SUPPLY VOLTAGE: VS = 6 VS = 15 1000 TA = 25oC, f = 1kHz SUPPLY VOLTAGE: VS = 6 VS = 15 IABC = 100A IABC = 30A IABC = 10A 100 10 MINIMUM 10 1 IABC = 1A 1 -50 -25 0 25 50 75 100 125 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) TEMPERATURE (oC) FIGURE 11. FORWARD TRANSCONDUCTANCE vs AMPLIFIER BIAS CURRENT FIGURE 12. FORWARD TRANSCONDUCTANCE vs TEMPERATURE 3-5 CA3060 Typical Performance Curves 100 FORWARD TRANSCONDUCTANCE (mS) IABC = 100A -50 PHASE ANGLE (DEGREES) 10 IABC = 10A IABC = 1A 1.0 -100 -150 -200 -250 0.1 TA = 25oC SUPPLY VOLTAGE: VS = 6 VS = 15 0.01 0.1 1.0 IABC = 10A IABC = 1A 10 -300 -350 (Continued) 0 10,000 TA = 25oC, f = 1kHz SUPPLY VOLTAGE: VS = 6 VS = 15 1000 INPUT RESISTANCE (k) 100 TYPICAL 10 1 10 MINIMUM 100 1000 0.01 0.001 100 PHASE ANGLE FORWARD TRANS. FREQUENCY (MHz) AMPLIFIER BIAS CURRENT (A) FIGURE 13. FORWARD TRANSCONDUCTANCE vs FREQUENCY 1000 TA = 25oC, f = 1kHz OUTPUT RESISTANCE (M) SUPPLY VOLTAGE: VS = 6 VS = 15 100 FIGURE 14. INPUT RESISTANCE vs AMPLIFIER BIAS CURRENT 7.0 BIAS REGULATOR VOLTAGE (V) TA = 25oC SUPPLY VOLTAGE: VS = 6 VS = 15 TYPICAL 6.75 10 6.5 TYPICAL 1 1 10 100 1000 AMPLIFIER BIAS CURRENT (A) 6.25 0 200 400 600 800 1000 1200 1400 BIAS REGULATOR CURRENT (A) FIGURE 15. OUTPUT RESISTANCE vs AMPLIFIER BIAS CURRENT FIGURE 16. BIAS REGULATOR VOLTAGE vs BIAS REGULATOR CURRENT Test Circuit RF V+ INPUT RS 13 RC CC 14 8 RB RZ RABC I2 V2 IABC + 1 VZ is measured between Terminal 1 and 8 VABC is measured between Terminals 15 and 8 3 OUTPUT EXTERNAL LOAD - V Z - VA BC [ ( V+ ) - ( V- ) - 0.7 ] R Z = ----------------------------------------------- , R ABC = ---------------------------I2 I ABC 16 AMPLIFIER 1 15 Supply Voltage: For both 6V and 15V TYPICAL SLEW RATE TEST CIRCUIT PARAMETERS IABC A 100 10 1 SLEW RATE V/s 8 1 0.1 I2 A 200 200 2 RABC 62K 620K 6.2M RS 100K 1M 10M RF 100K 1M 10M RB 51K 510K 5.1M RC 100 1K CC F 0.02 0.005 0 13 pF 10 M FIGURE 17. SLEW RATE TEST CIRCUIT FOR AMPLIFIER 1 OF CA3060 3-6 CA3060 Application Information The CA3060 consists of three operational amplifiers similar in form and application to conventional operational amplifiers but sufficiently different from the standard operational amplifier (op amp) to justify some explanation of their characteristics. The amplifiers incorporated in the CA3060 are best described by the term Operational Transconductance Amplifier (OTA). The characteristics of an ideal OTA are similar to those of an ideal op amp except that the OTA has an extremely high output impedance. Because of this inherent characteristics the output signal is best defined in terms of current which is proportional to the difference between the voltages of the two input terminals. Thus, the transfer characteristics is best described in terms of transconductance rather than voltage gain. Other than the difference given above, the characteristics tabulated are similar to those of any typical op amp. The OTA circuitry incorporated in the CA3060 (Figure 18) provides the equipment designer with a wider variety of circuit arrangements than does the standard op amp; because as the curves indicate, the user may select the optimum circuit conditions for a specific application simply by varying the bias conditions of each amplifier. If low power consumption, low bias, and low offset current, or high input impedance are primary design requirements, then low current operating conditions may be selected. On the other hand, if operation into a moderate load impedance is the primary consideration, then higher levels of bias may be used. Q11 Q7 Q10 Q3 INVERTING INPUT D2 Q2 D3 Q4 Q5 + Q9 D8 D7 Q14 D5 D6 V+ Q15 In addition, the high output impedance makes these amplifiers ideal for applications where current summing is involved. The design of a typical operational amplifier circuit (Figure 19) would proceed as follows: Circuit Requirements Closed Loop Voltage Gain = 10 (20dB) Offset Voltage Adjustable to Zero Current Drain as Low as Possible Supply Voltage = 6V Maximum Input Voltage = 50mV Input Resistance = 20k Load Resistance = 20k Device: CA3060 +6V 0.1 3 RS 20k INPUT 13 RF 200k AMPLIFIER 1 16 RL 20k +6V 14 ROFFSET <4M 2.2M + 8 15 18k -6V 0.1 -6V RABC 560k TO +6V FIGURE 19. 20dB AMPLIFIER USING THE CA3060 Calculation 1. Required Transconductance g21. Assume that the open loop gain AOL must be at least ten times the closed loop gain. Therefore, the forward transconductance required is given by: g21 = AOL/RL = 100/18k 5.5mS (RL = 20k in parallel with 200k 18k) 2. Selection of Suitable Amplifier Bias Current. The amplifier bias current is selected from the minimum value curve of transconductance (Figure 11) to assure that the amplifier will provide sufficient gain. For the required g21 of 5.5mS an amplifier bias current IABC of 20A is suitable. - Q13 OUTPUT Q12 AMPLIFIER BIAS CURRENT (ABC) D1 VQ1 NONINVERTING INPUT Q6 Q8 D4 COMPLETE OTA CIRCUIT V- FIGURE 18. COMPLETE SCHEMATIC DIAGRAM SHOWING BIAS REGULATOR AND ONE OF THE THREE OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS Bias Consideration for Op Amp Applications The operational transconductance amplifiers allow the circuit designer to select and control the operating conditions of the circuit merely by the adjustment of the amplifier bias current IABC. This enables the designer to have complete control over transconductance, peak output current and total power consumption independent of supply voltage. 3. Determination of Output Swing Capability. For a closed loop gain of 10 the output swing is 0.5V and the peak load current is 25A. However, the amplifier must also supply the necessary current through the feedback resistor and if RS = 20k, then RF = 200k for ACL = 10. Therefore, the feedback loading = 0.5V/200k = 2.5A. The total amplifier current output requirements are, therefore, 27.5A. Referring to the data given in Figure 5, we see that for an amplifier bias current of 20A the amplifier output current is 40A. This is obviously adequate and it is not necessary to change the amplifier bias current IABC. 3-7 CA3060 4. Calculation of Bias Resistance. For minimum supply current drain the amplifier bias current IABC should be fed directly from the supplies and not from the bias regulator. The value of the resistor RABC may be directly calculated using Ohm's law. V SUP - VA BC R ABC = -----------------------------------I ABC 12 - 0.63 R ABC = ------------------------6 20 x 10 R ABC = 568.5k or 560k 0 RELATIVE GAIN (dB) -20 RL = 10k CL = 0 -40 -60 RL = 10k CL = 15pF -80 0.01 0.1 1.0 10 100 5. Calculation of Offset Adjustment Circuit. In order to reduce the loading effect of the offset adjustment circuit on the power supply, the offset control should be arranged to provide the necessary offset current. The source resistance of the non-inverting input is made equal to the source resistance of the inverting input, i.e., 20k x 200k --------------------------------------- 18k 20k + 200k FREQUENCY (MHz) FIGURE 20. EFFECT OF CAPACITIVE LOADING ON FREQUENCY RESPONSE A 1000 B C D E F G H PEAK OUTPUT CURRENT (mA) 100 I J 10 K L 1 Because the maximum offset voltage is 5mV plus an additional increment due to the offset current (Figure 2) flowing through the source resistance (i.e., 200 x 10-9 x 18 x 103V), the Offset Voltage Range = 5mV + 3.6mV = 8.6mV. The current necessary to provide this offset is: 8.6mV ----------------- 0.48A 18k With a supply voltage of 6V, this current can be provided by a 10M resistor. However, the stability of such a resistor is often questionable and a more realistic value of 2.2M was used in the final circuit. Capacitance Effects The CA3060 is designed to operate at such low power levels that high impedance circuits must be employed. In designing such circuits, particularly feedback amplifiers, stray circuit capacitance must always be considered because of its adverse effect on frequency response and stability. For example a 10k load with a stray capacitance of 15pF has a time constant of 1MHz. Figure 20 illustrates how a 10k 15pF load modifies the frequency characteristic. Capacitive loading also has an effect on slew rate; because the peak output current is established by the amplifier bias current, IABC (Figure 5), the maximum slew rate is limited to the maximum rate at which the capacitance can be charged by the IOM. Therefore, SR = dv/dt = IOM/CL, where CL is the total load capacitance including strays. This relationship is shown graphically in Figure 21. When measuring slew rate for this data sheet, care was taken to keep the total capacitive loading to 13pF. 0.01 0.1 1.0 SLEW RATE (V/s) 10 100 A. CL = 10,000pF B. CL = 3,000pF C. CL = 1000pF D. CL = 300pF E. CL = 100pF F. CL = 30pF G. CL = 10pF H. CL = 3pF I. CL = 1pF J. CL = 0.3pF K. CL = 0.1pF L. CL = 0.03pF FIGURE 21. EFFECT OF LOAD CAPACITANCE ON SLEW RATE Phase Compensation In many applications phase compensation will not be required for the amplifiers of the CA3060. When needed, compensation may easily be accomplished by a simple RC network at the input of the amplifier as shown in Figure 17. The values given in Figure 17 provide stable operation for the critical unity gain condition, assuming that capacitive loading on the output is 13pF or less. Input phase compensation is recommended in order to maintain the highest possible slew rate. In applications such as integrators, two OTAs may be cascaded to improve current gain. Compensation is best accomplished in this case with a shunt capacitor at the output of the first amplifier. The high gain following compensation assures a high slew rate. 3-8 CA3060 Typical Applications Having determined the operating points of the CA3060 amplifiers, they can now function in the same manner as conventional op amps, and thus, are well suited for most op amp applications, including inverting and non-inverting amplifiers, integrators, differentiators, summing amplifiers etc. Circuit Description Figure 23 shows the block diagram of a tri-level comparator using the CA3060. Two of the three amplifiers are used to compare the input signal with the upper limit and lower limit reference voltages. The third amplifier is used to compare the input signal with a selected value of intermediate limit reference voltage. By appropriate selection of resistance ratios this intermediate limit may be set to any voltage between the upper limit and lower limit values. The output of the upper limit and lower limit comparator sets the corresponding upper or lower limit flip-flop. The activated flip-flop retains its state until the third comparator (intermediate limit) in the CA3060 initiates a reset function, thereby indicating that the signal voltage has returned to the intermediate limit selected. The flip-flops employ two CA3086 transistor array ICs, with circuitry to provide separate "SET" and "POSITIVE OUTPUT" terminals. Tri-Level Comparator Tri-level comparator circuits are an ideal application for the CA3060 since it contains the requisite three amplifiers. A trilevel comparator has three adjustable limits. If either the upper lower limit is exceeded, the appropriate output is activated until the input signal returns to a selected intermediate limit. Tri-level comparators are particularly suited to many industrial control applications. V+ = 6V INPUT SIGNAL (ES) 1 V+ = 6V 20K 3 REGULATOR IN CA3060 2 25K 15 13K EU 5.1K 14 5.1K 13 R4 10K R2 1K UPPER LIMIT REFERENCE VOLTAGE 5.1K 12 + 1/3 CA3060 16 WHEN UPPER LIMIT IS EXCEEDED IABC 8 V+ = 6V SATURATES WHEN UPPER LIMIT IS EXCEEDED 100 LOAD 8 6 7 Q1 CA3086 10K 5.1K 4.7K V- = -6V SET 11 9 10 4 5 1 2 150K 10 IABC 3 UPPER LIMIT FLIP-FLOP 13 12 14 1/3 CA3060 + 9 RESET WHEN INTERMEDIATE REFERENCE LIMIT IS EXCEEDED V+ = 6V SATURATES WHEN LOWER LIMIT IS EXCEEDED 100 LOAD 4.7K IABC 10K 6 7 8 Q2 11 INTERMEDIATE LIMIT REFERENCE VOLTAGE R3 10K LOWER LIMIT REFERENCE VOLTAGE EL 5.1K 5 EU - EL 2 6 5.1K 4 CA3086 150K 1/3 CA3060 + 7 SET 10 WHEN LOWER LIMIT IS EXCEEDED 11 9 4 5 1 2 5.1K 3 LOWER LIMIT FLIP-FLOP 12 14 13 R1 1K NOTES: 9. Items in dashed boxes are external to the CA3086. All resistance values are in ohms. 10. E > E = Q (ON), Q (OFF) S U 1 2 E L < E U = Q 2 (ON), Q 1 (OFF) EU - EL E S < ------------------- = Q 1 (OFF), Q 2 (OFF) 2 FIGURE 22. TRI-LEVEL COMPARATOR CIRCUIT 3-9 CA3060 V+ CA3060 TRI-LEVEL DETECTOR UPPER LIMIT REFERENCE VOLTAGE INPUT SIGNAL INTERMEDIATE LIMIT REFERENCE VOLTAGE LOWER LIMIT REFERENCE VOLTAGE + Active Filters - Using the CA3060 as a Gyrator The high output impedance of the OTAs makes the CA3060 ideally suited for use as a gyrator in active filter applications. Figure 24 shows two OTAs of the CA3060 connected as a gyrator in an active filter circuit. The OTAs in this circuit can make a 3F capacitor function as a floating 10kH inductor across Terminals A and B. The measured Q of 13 (at a frequency of 1Hz) of this inductor compares favorably with a calculated Q of 16. The 20k to 2M attenuators in this circuit extend the dynamic range of the OTA by a factor of 100. The 100k potentiometer, across V+ and V-, tunes the inductor by varying the g21 of the OTAs, thereby changing the gyration resistance. V+ SET CA3086 FLIP-FLOP POSITIVE OUTPUT (WHEN UPPER LIMIT IS REACHED) V+ SET CA3086 FLIP-FLOP POSITIVE OUTPUT (WHEN LOWER LIMIT IS REACHED) - + RESET - + V- FIGURE 23. FUNCTIONAL BLOCK DIAGRAM OF A TRI-LEVEL COMPARATOR Three Channel Multiplexer Figure 25 shows a schematic of a three channel multiplexer using a single CA3060 and a 3N153 MOSFET as a buffer and power amplifier. V+ = 15V V+ = 15V The circuit diagram of a tri-level comparator appears in Figure 22. Power is provided for the CA3060 via terminal 3 and 8 by 6V supplies and the built-in regulator provides amplifier bias current (IABC) to the three amplifiers via terminal 1. Lower limit and upper limit reference voltages are selected by appropriate adjustment of potentiometers R1 and R2, respectively. When resistors R3 and R4 are equal in value (as shown), the intermediate limit reference voltage is automatically established at a value midway between the lower limit and upper limit values. Appropriate variation of resistors R3 and R4 permits selection of other values of intermediate limit voltage. Input signal (ES) is applied to the three comparators via terminals 5, 12 and 14. The "SET" output lines trigger the appropriate flip-flop whenever the input signal reaches a limit value. When the input signal returns to an intermediate value, the common flip-flop "RESET" line is energized. The loads in the circuits, shown in Figure 22 are 5V, 25mA lamps. V+ = 6V TERMINAL A 3 20k 14 20k 13 15 560k L = 10kH 2M 560k 10 V3F 12 9 AMP 2 11 8 TERMINAL B 2M V- = -6V 100k 20 k 20 k V+ AMP 1 16 3 2k 4 2k 5 + 8 6 300k STROBE 2k 12 2k 11 + 0.02 F V- = -15V 0.01F 7 3N153 9 3 390 10 0.001F OUTPUT 4 2 300k STROBE 2k 13 2k 14 + 16 3k V- = -15V 15 300k STROBE +15V STROBE "ON" -15V STROBE "OFF" FIGURE 25. THREE CHANNEL MULTIPLEXER FIGURE 24. TWO OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS OF THE CA3060 CONNECTED AS A GYRATOR IN AN ACTIVE FILTER CIRCUIT When the CA3060 is connected as a high input impedance voltage follower, and strobe "ON", each amplifier is activated and the output swings to the level of the input of the amplifier. The cascade arrangement of each CA3060 amplifier with the MOSFET provides an open loop voltage gain in excess of 100dB, thus assuring excellent accuracy in the voltage follower mode with 100% feedback. Operation at 6V is also possible with several minor changes. First, the resistance in series with the amplifier bias current (IABC) terminal of each amplifier should be decreased to maintain 100A of strobe "ON" current at this lower supply voltage. Second, the drain resistance for the MOSFET should be 3-10 CA3060 decreased to maintain the same value of source current. The low cost dual gate protected MOSFET, 40841 type, may be used when operating at the low supply voltage. The phase compensation network consists of a single 390 resistor and a 1000pF capacitor, located at the interface of the CA3060 output and the MOSFET gate. The bandwidth of the system is 1.5MHz and the slew rate is 0.3V/s. The system slew rate is directly proportional to the value of the phase compensation capacitor. Thus, with higher gain settings where lower values of phase compensation capacitors are possible, the slew rate is proportionally increased. and 3 is shown in Figure 27 and a typical circuit is shown in Figure 28. The multiplier consists of a single CA3060 and, as in the two quadrant multiplier, exhibits no level shift between input and output. In Figure 27, Amplifier 1 is connected as an inverting amplifier for the X-input signal. The output current of Amplifier 1 is calculated as follows: IO(1) = [-VX] [g21(1)] EQ. 1 Amplifier 2 is a non-inverting amplifier so that IO(2) = [+VX] [g21(2)] EQ. 2 Non-Linear Applications AM Modulator (Two Quadrant Multiplier) Figure 26 shows Amplifier 3 of the CA3060 used in an AM modulator or two quadrant multiplier circuit. When modulation is applied to the amplifier bias input, Terminal B, and the carrier frequency to the differential input, Terminal A, the waveform, shown in Figure 26 is obtained. Figure 26 is a result of adjusting the input offset control to balance the circuit so that no modulation can occur at the output without a carrier input. The linearity of the modulator is indicated by the solid trace of the superimposed modulating frequency. The maximum depth of modulation is determined by the ratio of the peak input modulating voltage to V-. The two quadrant multiplier characteristic of this modulator is easily seen if modulation and carrier are reversed as shown in Figure 26. The polarity of the output must follow that of the differential input; therefore, the output is positive only during, the positive half cycle of the modulation and negative only in the second half cycle. Note, that both the input and output signals are referenced to ground. The output signal is zero when either the differential input or IABC are zero. Four Quadrant Multiplier The CA3060 is also useful as a four quadrant multiplier. A block diagram of such a multiplier, utilizing Amplifiers 1, 2 Because the amplifier output impedances are high, the load current is the sum of the two output currents, for an output voltage VO = VXRL [g21(2) - g21(1)] EQ. 3 The transconductance is approximately proportional to the amplifier bias current; therefore, by varying the bias current the g21 is also controlled. Amplifier 2 bias current is proportional to the Y-input signal and is expressed as ( V- ) + V Y I ABC(2) -----------------------R1 EQ. 4 Hence, g21(2) k [(V-) + VY] EQ. 5 Bias for Amplifier 1 is derived from the output of Amplifier 3 which is connected as a unity gain inverting amplifier. IABC(1), therefore, varies inversely with VY. And by the same reasoning as above EQ. 6 g21(1) k [(V-) - VY] Combining Equations 3, 5 and 6 yields: VO VX x k x RL {[(V-) + VY] - [(V-) - VY]} or VO 2kRLVXVY +6V 3 CARRIER TERM. A 4 10k 1k 5 1k 1M 6 -6V V+ MODULATION TERM. B 10k 100k V1M + 8 AMP 3 7 100k MODULATED OUTPUT FIGURE 26. TWO QUADRANT MULTIPLIER CIRCUIT USING THE CA3060 WITH ASSOCIATED WAVEFORMS 3-11 CA3060 + X INPUT IABC (1) + AMP 1 R1 RL VO X INPUT CA3060 1M 13 IO(2) R2 270 RF Y INPUT RIN Y INPUT 1M 270 100 AMP 1 16 1M 15 14 200k 51k 4 100 0.02F 24k 1.1M 10 11 12 5 AMP 3 7 240k 6 3 V+ 100k 100k V4 51 k 560k 270 1M OUTPUT IO(1) Figures 29B and 29C, respectively, show the squaring of a triangular wave and a sine wave. Notice that in both cases the output is always positive and returns to zero after each cycle. - AMP 2 IABC (2) + AMP 3 FIGURE 27. FOUR QUADRANT MULTIPLIER Figure 28 shows the actual circuit including all the adjustments associated with differential input and an adjustment for equalizing the gains of Amplifiers 1 and 2. Adjustment of the circuit is quite simple. With both the X and Y voltages at zero, connect Terminal 10 to Terminal 8. This procedure disables Amplifier 2 and permits adjusting the offset voltage of Amplifier 1 to zero by means of the 100k potentiometer. Next, remove the short between Terminal 10 and 8 and connect Terminal 15 to Terminal 8. This step disables Amplifier 1 and permits Amplifier 2 to be zeroed with the other potentiometer. With AC signals on both the X and Y inputs, R3 and R11 are adjusted for symmetrical output signals. Figure 29 shows the output waveform with the multiplier adjusted. The voltage waveform in Figure 29A shows suppressed carrier modulation of 1kHz carrier with a triangular wave. AMP 2 9 560k 8 270 FIGURE 28. TYPICAL FOUR QUADRANT MULTIPLIER CIRCUIT FIGURE 29A. FIGURE 29B. FIGURE 29C. FIGURE 29. VOLTAGE WAVEFORMS OF FOUR QUADRANT MULTIPLIER CIRCUIT 3-12 |
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